The present invention relates to a semiconductor device, a memory access control method, and a semiconductor device system.
An operation circuit such as a CPU (Central Processing Unit), for example, accesses an external memory (main memory) such as an SDRAM (Synchronous Dynamic Random Access Memory) and reads or writes data. It should be noted that when the operation circuit accesses the external memory, an access delay called “latency” occurs. The latency is one of the performance indices of the external memory, and CAS (Column Address Strobe) latency or the like is typical latency. The smaller the latency is, the faster the access can be performed.
The external memory usually supports burst access in which a plurality of addresses are successively accessed by designating one address in addition to random access in which addresses are designated one by one and access is repeatedly performed. The above-mentioned access delay occurs for each address designation. If the plurality of successively-accessed addresses in the burst access are addresses that are actually going to be accessed from now (hereinafter referred to as “target addresses”), the number of times of the address designation can be reduced compared to that in the random access. Therefore, the number of occurrences of the access delay can also be reduced, thus improving the access efficiency.
Japanese Unexamined Patent Application Publication No. H09-198305 discloses a memory control apparatus in which when an address A is first accessed and then an address B is accessed, a time necessary for the burst access is compared with a time necessary for the random access, and the access method having a shorter necessary time is selected.